1. Field of the Invention
The present invention relates to a test device for defect inspection, and more particularly to a test device for VC mode defect inspection by using at least one charged particle beam.
2. Description of the Prior Art
Undoubtedly, compared to any other technology or knowledge, semiconductor devices not only impact nowadays society but also influence our daily life. Although it can be traced to two centuries ago, for example Alessandro Volta in 18th century and Michael Faraday in 19th century, the history of semiconductor development indeed influences mankind in commercial semiconductor devices is 20th century. In the first, vacuum tube transistor is replaced by the semiconductor devices which mainly include BJT (Bipolar Junction Transistor) and MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), and then the semiconductor devices are minimized into integrated circuits. No matter digital logic circuit device, analog circuit device or communication devices, these semiconductor devices can be fabricated on silicon-based substrate or semiconductor compound substrate. Another semiconductor devices are photoelectronic devices which mostly include LED (Light Emitting Diode), LD (LASER Diode) or photovoltaic cell base on photoelectric effect. Currently, digital electronic devices based on MOSFET fabricated in silicon substrate are commercially the most significant, and the applications of the devices are processors and memory devices.
Fabrication processes for manufacturing ICs in the silicon substrate include cleaning process, oxidation and thermal process, ion-implementation process, thin film deposition, lithography, etching process and CMP (Chemical Mechanical Polishing) process. By the combination of the above processes, when all electronic devices are formed in the substrate, and then followed by metallization process to electrically connect all electronic devices, a specific application device, such as CPU, ASIC, FPGA, DRAM, or Flash, can be produced. With the technology progress of semiconductor process, the smaller width of an electronic device followed by Moore's law which means transistors are doubled every 18 to 24 months, the more devices in one wafer can be fabricated to cost down.
The semiconductor fabrication processes include ion implantation process, thermal process, thin film deposition process, etching process, CMP (Chemical Mechanical Polishing) process, lithography, and cleaning process. And they will be briefed hereinafter.
Ion-implantation process will direct group III or group V atoms implanted into silicon substrate to alter local electric conductivity such that some regions are positive conductivity and some regions are negative conductivity. Phosphorus or Arsenic atoms are usually used for the negative conductivity, while Boron atom is usually used for the positive conductivity.
Thermal process provides formation of thermal oxide layer and annealing for drive-in after ion-implantation. In the present art, RTP (Rapid Thermal Process) is popular instead of conventional thermal process in furnace. It includes RTO (Rapid Thermal Oxidation) and RTA (Rapid Thermal Annealing) to respectively form silicon oxide and repair lattice damages after ion-implantation such that single crystal structure can be recovered and dopant can be activated.
Thin film deposition process includes PVD (Physical Vapor phase Deposition) and CVD (Chemical Vapor phase Deposition) to form several to several tens thin film layers with variant materials and thicknesses on silicon substrate. Metal layers, formed on a substrate, always provide electric interconnections among devices, while dielectric layer provides isolation between metal layers. Chemical reactions in vapor phase, happened to form thin films in CVD, include MOCVD (Metal-Organic CVD), APCVD (Atmosphere Pressure CVD), LPCVD (Low Pressure CVD), HPCVD (Hybrid Physical CVD), RTCVD (Rapid Thermal CVD), HDPCVD (High Density Plasma CVD), and PECVD (Plasma Enhanced CVD). Thin films forms by CVD usually include silicon oxide, silicon nitride, polysilicon, metal tungsten, metal aluminum, and metal titanium nitride. Metal target are heated or bombarded in vacuum such that atoms on the metal target can be transferred to substrate surface to form thin film in PVD, which includes evaporation and sputtering. Metal thin films, such as aluminum, titanium, or alloy thereof, are always formed by using PVD. Quality control of the thin film is critical to IC process, so thin film process must be monitored throughout the procedure to reflect abnormal, such that thickness uniformity and defect and be avoided.
Etching process, which includes wet etch and dry etch, is to remove material. In the semiconductor process, patterns on a reticle can be transferred to a thin film by using etch process. Wet etching is isotropic by reacting etchant to selective material, and etched profile always reveals bowl-like shape. Dry etch is popular and anisotropic by reacting plasma in an external electric field with the selective material, and etched profile will reveal vertical-like shape.
CMP is another method to remove material, which introduce slurry between polish pad and wafer with chemical and mechanical reactions to achieve whole wafer planation, such that thin films in the following process can be formed better. Silicon oxide layer, metal layer and polysilicon layer are most applied in the CMP process.
Lithography process, also named photo-lithography process, is the most critical in the semiconductor process, which includes PR (photo Resist) layer coating, soft bake, exposure, development, hard bake, and ash after etching process. The PR can be selectively removed through exposure and development, and circuit patterns can be transferred to a specific material. When the semiconductor process continues shrinking, available RET (Resolution Enhancement technology), such as OPC (Optical Proximity Correction), immersion lithography, and EUV (Extreme Ultraviolet lithography, are applied.
Cleaning process must be processed after all other process recited above to avoid uninvited particles or residues to impact device quality, which includes rinsing wafer by DI (De-Ionized) water and drying the wafer. Ultrasonic agitation can be applied in the cleaning process. This process will clean out all pollutions, such as particles, organic matter, inorganic matter, metal ions.
Defects are inevitably generated in the semiconductor process, which will greatly impact device performance, even failure. Device yield is thus impacted and cost is raised. Current defects can be classified into systematic defects and random defects in general. On the one hand, system defects infer defects will be found repeatedly and systematically in wafers, in which defect patterns can be used as reference in classification to determine root cause of which process incurs such defects. In order to increase semiconductor process yield, it is critical to enhance yield by monitoring, such as by using SEM (Scanning Electron Microscope), systematic defects highly appeared regions in mass production process to real time eliminate systematic defects. On the other hand, the non-systematic defects, random particle defects, are random residues left in wafers. Distributions and characteristic profiles are important references to distinguish systematic defects from non-systematic defects.
More specifically, systematic defects can be classified as reticle errors in alignment or machine offset, process mistakes incurred by recipes or materials, prober damages in wafer probing, scratches on wafer surface, and wafer edge effect of topography incurred from non-uniformity of PR coating or thermal stress.
The corresponding defects are recited hereinafter in brief. Defects incurred in lithographic process include PR residue defects due to PR deteriorated or impurity, peeling defects, bridge defects, bubble defects, and dummy pattern missing defects due to pattern shift. Defects incurred in etching process include etching residue defects, over-etching defects and open circuit defect. Defects incurred in CMP process include slurry residue defects, dishing defects and erosion defects due to variant polishing rates, scratched due to polishing. Further, when process nodes continue shrinking, new materials and processes will be introduced to inevitably incur new type defects. For example, because physical dimension of patterns are smaller than the optical resolution of the applied lithographic wavelength (193 nm), the critical dimension exposed on wafers may incur offset. Thinning defects are another inevitably incurred in the process node shrinking. In order to reduce RC delay in multi-layered interconnection structures, low-k dielectric layer and cupper material are introduced. Cupper can't be etched and hence damascene process is introduced that metal is filled into dielectric layer. Therefore, some other hidden defects are covered under layer, such as void defects, etching residue defects, over-etching defect, under layer particles, and via open incurred in the interconnection process. Such hidden, crucial defects are too hard to be analyzed and eliminated.
For the non-systematic defects are mainly random particles defect incurred from particles in air randomly fallen on the wafer, which are not easy to be identified and resolved.
In order to enhance semiconductor process yield, defects have to be identified as soon as possible to prevent from impact pouring out. Optical microscope is used in conventional optical inspection which includes bright field inspection and dark field inspection. Every die on a wafer is scanned by optical beam and images of every die are generated and stored.
When semiconductor nodes continue shrinking, dimensions of defect shrink also. Unimportant small defects in previous now become critical therefore. It is a challenge to identify such small defects by using conventional optical inspection tool and a new tool is necessary. One method is to combine the operations of optical inspection and review SEM. Because of resolution, the optical inspection is not enough to meet requirement of identifying defects, but a suspect region in blurred images can be determined defect-like and reviewed by review SEM with high resolution. Thus defects can be identified and analyzed. Another method is to illuminate dual beams on a wafer surface to obtain interference patterns, and defect regions always have different interference pattern to that of the normal region. Thus, defects can be identified and further analyzed by review SEM. In practice, defects must be identified first and locations of the defects are forward to review SEM with high resolution to analyze defects.
The ebeam inspection tool is to find or identify defects in the semiconductor process, and relative to review SEM, a large FOV (Field-of-View) and large beam current are commercial means to enhance inspection throughput. In order to obtain large FOV, a SORIL (Swing Objective Retarding Immersion Lens) system is applied commercially. Moreover, resolution is sometimes lowered, compared to review SEM, enough to capture defects.
The ebeam inspection tool is designed different from the review SEM. The review SEM is designed to known, identified defects or suspects of defect, so scan duration is long enough to analyze or review defects, and hence it can't process inspection. On the other hand, the ebeam inspection tool, with high scanning rate than the review SEM and high resolution than the optical inspection tool, can identify defects that the optical inspection tool in no way to capture.
Furthermore, in lithographic process, some particular patterns may have great possibility to incur defects, but won't incur them each time. The defects generated by these particular patterns even can't be modified through recipe tuning or modifying reticle directly. Such a kind of patterns is named hot spot, and must be monitored in-line process.
Applications of SEM, except yield management tool of ebeam inspection and analysis tool of review SEM, may further be metrology tool in semiconductor manufacturing process; that is CD (critical Dimension)-SEM. CD-SEM will measure CD in a wafer with by line-scanning sample with moving stage to reveal process uniformity. Moreover, in order to obtain exact dimension, resolution is very critical, and thus low beam current must be applied.
Besides, one way to identify electric defects in the die is disclosed in the U.S. Pat. No. 4,204,155A, which provides a resistivity probe head, or a four-point probe, is used to directly contact the semiconductor device for obtaining the defect results.
Another prior art, TW patent 430,906, discloses another way to monitor and inspect cross-contamination of the conventional technique, which is a four-point probe method. The cross-contamination is caused by the ion implantation which produces unexpected dopants in the wafer, and the concentration of the unexpected dopants is usually so high that the electricity of a wafer becomes abnormal. Further, the wafer will be scrapped by the four-point probe easily.
In conclusion, both the two prior arts aforementioned can only provide electrical characteristic results; that is, the tested results only come from the electrically contact between the four-point probe and the test circuit configured in the scribe line within a die. However, since the fabrication process of the test circuit is different from that of the die, the test result of the test circuit configured in the scribe line may be actually different from that of the die itself. Thus, the test result is not so precise enough and is unreliable as well. Hence, one accurate and reliable test method or structure for testing the die is necessary.